There is a constant drive within the semiconductor industry to increase the quality, reliability, performance, and throughput and to reduce the cost of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive has resulted in improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Reduction in defects in the manufacture of the components of a typical transistor lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Improved performance capability of integrated circuit devices has been obtained by increasing the operating speed of transistors. Greater operating speed is related to decreasing the gate length of the transistors. However, decreases in gate length require scaling down of the entire device, thereby reducing the thicknesses of the gate dielectric (Gox) and the inter-layer dielectric (ILD).
To insure the reliability of the Gox and ILD layers, semiconductor manufacturers typically conduct several tests. One such test evaluates the qualities and capabilities of the dielectric layers by determining the time-dependent dielectric breakdown (TDDB) of the layers. The Gox or ILD is subjected to a constant (DC) voltage stress over time and its “time to fail” is determined. The time at which the Gox or ILD breaks down is measured by detecting when a sudden leakage current short occurs, as evidenced by an abrupt increase in leakage current.
However, integrated transistors and interconnection wires are typically operated by rapid activation and deactivation of components (on/off mode), in contrast to application of a constant DC voltage bias. A much greater component lifetime should be expected than would be indicated by the above described TDDB test because less stress is imposed on the transistor with alternating on/off application of voltage. Thus conventional test setups that determine leakage short detection by application of a DC voltage present disadvantages.
A current solution is illustrated in FIG. 1. A mechanical switch is used to connect, alternately, between two different voltage levels, V1 and V2. For example, a V2 level of +20V may be applied to the circuit between alternate applications of ground (V1). During rapid switching between V1 and V2, AC oscillation occurs and leakage current cannot be measured. The test requires a period 101 in which constant DC voltage is applied, illustrated at the V2 level, inserted between periods 103 and 105 of rapid voltage switching. During the time period 101, which is typically in the order of about ten seconds, leakage current is sensed.
This method has several disadvantages. The manual voltage switching severely limits the AC frequency to a maximum of about 100 kilohertz (kHz), which is significantly lower than the typical operating frequency of about one gigahertz (GHz) for the semiconductor elements. Also, the manual voltage switching creates a detectable level of voltage overshoot. Moreover, any Gox or ILD breakdown that may occur during the AC stress periods 103 and 105 would not be detected at the time of breakdown, as sensing occurs during the application of constant DC voltage, period 101. The time to fail becomes subjective, since it depends on the duration set for the unsensed AC stress. If the AC stress period is set too long, the periodicity of leakage sense becomes very low, which affects the time resolution of the measurement and risks missing an important breakdown event during period 103 or period 105. If the AC stress is set too short, the 10 second DC sense duration becomes dominant and the AC component becomes less significant and, thereby, meaningless.
As leakage current is not measured while AC voltage bias is being applied, the degree of improvement of this method, compared with the constant DC TDDB method is speculative. With aggressive semiconductor scaling in terms of rapidly reducing the Gox and ILD layers, TDDB lifetime is currently one of the most critical limiting factors in pushing the operating limits of semiconductor chip products.
A need therefore exists for a method for more accurately determining the TDDB of Gox and ILD layers under conditions that mimic operating conditions, including application of AC voltage at a relatively high frequency.